Ruby Lake, Ansel Adams Wilderness

Analog Verification (4 Days)

This challenging four day course provides participants with the tools they need to take on the task of verifying complex analog, RF, and mixed-signal integrated circuits. It combines lecture with a substantial amount of time in the lab to teach the overall analog verification process. You will learn how to develop a verification plan, functional models of analog blocks, regression tests for those models, and a fully verified Verilog model for the entire analog portion of the design for use in chip-level verification.

Target Audience
The class is intended for anyone who would benefit from a working knowledge of analog verification or from improving their skills with Verilog-A/MS. These include: analog verification engineers, analog designers, analog design leads, and digital verification engineers and CAD engineers who meet the prerequisites.

Instructors
Ken Kundert and Henry Chang.

Prerequisites
Though not required, it is helpful if students have a working knowledge of Verilog-A, analog circuits and their design, and the Cadence design environment. The better prepared you are, the more you will get from the class.

Course Contents
Day 1 – Introduction and Block-Level Analog Modeling

• Introduction to analog verification
  
• Verification planning
  
• Review of Verilog-A
  
• Analog block-level functional modeling
  

Day 2 – Block-Level Mixed-Signal Modeling

• Review of Verilog
  
• Review of Verilog-AMS
  
• Mixed-signal block-level functional modeling
  
• Mixed-signal netlists
  
• Assertions
  

Day 3 – Block Level Analog Verification

• Block-level verification strategy
  
• Writing self-checking regression tests
  
• Techniques for testing common mixed-signal blocks
  
• Overcoming analog verification problems
  

Day 4 – System Level Analog Verification and Top-Down Design

• System-level verification strategy
  
• Verilog modeling of analog systems
  
• Verifying the top-level model
  
• Chip-level verification strategy
  
• Verification review
  

Days 1 & 2 are an in-depth refresher on Verilog, Verilog-A and Verilog-AMS, with an emphasis on best practices. Day 3 is often overlooked, but it is perhaps the most important day. It is where we teach you to create automated regression tests that throughly exercise and verify mixed-signal designs. It is a very unique aspect of this class. On day 4 we cover chip/analog subsystem level connectivity, function checking, and how to write Verilog models for chip level verification, with a focus on not only how to make them very efficient, but also how to assure that they are functionally equivalent to the circuit.

The class is structured to alternate between lecture and labs, with a large percentage of the class dedicated to rather open ended labs. In this way, everyone is challenged and learns a great deal, regardless of their experience level. People that are new to Verilog-AMS often just use the labs to gain experience with the language and simulator. Those with a lot of experience with the language challenge themselves more with the verification aspects.

Introduction to Analog Verification (2 days)

This two day course provides an in depth introduction to the verification of complex analog, RF, and mixed-signal integrated circuits. It combines lecture with labs to illustrate the concepts in analog verification. You will learn the principles of analog verification and the basics so that you can effectively interact with analog verification engineers such as working with them to develop the verification plan, understanding analog verification terminology, and gaining some ability to read the models and regression tests they create.

Target Audience
Those who want to get a solid introduction to analog verification- design managers, design leads, digital verification engineers, analog designers, CAD engineers; anyone who needs to work with analog verification engineers; and those considering becoming analog verification engineers

Instructors
Ken Kundert and Henry Chang.

Prerequisites
Students should have some knowledge of analog circuits. Knowing how to use the Cadence design environment is helpful. Experience in modeling with Verilog, Verilog-A, and Verilog-AMS is a plus, but it is not necessary. The better prepared you are, the more you will get from the class.

Course Contents
Day 1 – Introduction and Modeling

• Introduction to Analog Verification
• Getting started with the Modeling Languages
• Mixed-Signal Block Level Functional Modeling

Day 2 – Regression Testing

• Verification Planning
• Block level self checking regression tests
• System-level verification
• Wrap-up

Day 1 provides an introduction to analog verification. This is followed by a lecture on the subset of Verilog, Verilog-A, and Verilog-AMS that we commonly use in Analog Verification. This lecture on the behavioral modeling languages assumes that you have no prior experience with any of these languages. However, this lecture will likely seem fast paced if you, indeed, have no background. This is followed by a talk on how an AV engineer writes models for functional verification. Our goal is to provide sufficient information so that at the end of the class you are able to read, maybe modify slightly, a model or regression test that an AV engineer, trained by us, has written.

Day 2 continues the introduction to analog verification by discussing verification planning. We give a fairly comprehensive lecture on this subject, because it is in verification planning that there is a great deal of active engagement between the members of the design team and the analog verification engineers. Developing a good verification plan up front is key to ensuring that you verify what you want, that it is done in an efficient manner, and that the effort can be completed. We then discuss block level self checking regression testing and finally discuss how to verify at the chip and system level. Again, the emphasis here is to give you an understanding of what the AV engineer is trying to accomplish. In this way, you can better interact with the AV engineers, but also, by understanding what the AV engineer will be verifying, you can leverage their work potentially saving you effort as you work on the design.

Unlike the four day class, the majority of the time is spent in lecture. However, we do provide 3 labs – one on using block level functional models, one on runing block level regression tests, and one at running system level simulations.

Please feel free to call us or to send us e-mail if you are unsure which class is the most appropriate for you.

Cancellation
In the event that you have to cancel, half of the class fee will be refunded if we receive the cancellation notice 4 weeks prior to the start of the class.  Within 4 weeks of the start of the class, no refunds will be given.

Class terms and conditions.

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If you are interested in taking one of our public clasess or are interested in arranging a private class to be held at your facilities, please contact us.