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challenges
We can no longer live with the respins.  We need a better way.

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Analog Designs Have Changed

Whereas we used to design op-amps, we now design multi-mode wireless transceivers. And while the scale of the designs has obviously grown fantastically, the character of the designs have changed just as much. Analog designs have hundreds of modes and thousands of settings. They implement sophisticated algorithms and contain blocks that are self calibrating and self adapting. In a word, they are complex. And while it is their performance that commands most of the attention of the people that design them, it is now their complexity that is the source of most of the catastrophic failures in their design. While this is a new situation for analog circuits, it has been true for digital circuits for many years. Digital design teams addressed this problem by adopting a strong functional verification methodology driven by verification engineers. Analog designs have now gotten to the point where analog design teams must do the same.

Transistor-Level Simulation Is Too Slow

Analog designers have traditionally relied on transistor-level circuit simulation to verify their circuits. However, today’s designs are so large that it may take several weeks to simulate a single aspect of a complete circuit. With a circuit that has multiple behavioral modes, each must be checked individually in order to expose all of the functional errors in the design. For a design that implements hundreds of modes and thousands of settings, this may require many months, and perhaps years, of simulation time. Switching to the so called “Fast” simulators can provide some relief, but they are still orders of magnitude too slow to be able to completely verify all modes and settings of a complex analog design. Perhaps the most troublesome aspect of relying on transistor-level simulation is that the regression tests development cannot begin until a first pass of the entire design is complete.

The Race Goes To The Swift

While analog verification is a proven methodology that is both efficient and effective, it is not in widespread use at this point. Conditions are only now getting to the point where its use is becoming essential. Adoption is slowed by the fact that it requires new skills in the design teams and because its importance is not yet recognized. Eventually everyone designing complex chips that involve analog will use this methodology. Nevertheless the current situation represents an important advantage to those that have mastered the methodology as it represents a substantial differentiator that could last for years.

How Is It Possible To Address These Challenges?

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