
The approach to Yosemite's Half Dome
Functional Verification
Our goal is to help our clients locate errors quickly, efficiently, and systematically from the beginning to the end of the design process. Using a rigorous analog/RF verification methodology that includes automated regression testing, errors can be found before they have any impact on the design or other designers. Our approach accelerates the design process, improves the quality of the design, creates designs that can be more easily re-used, and interestingly, allows designers more freedom and time for design and architectural exploration.
The first stage of the methodology is planning creating the verification, simulation, and modeling plans. The second stage is developing the models, testbenches, and setting up the regression tests. The third stage is to use the regression tests in the design loop. The plans, models, and testbenches are then improved as the design goes forward. The essence of our approach is to verify that the specifications, the schematics and any models produced such as a Verilog or VHDL model for system level verification are consistent throughout the design process.
Performance Verification
We employ deep experience and knowledge of the capabilities and characteristics of simulators and modeling languages as well as a strong understanding of circuit theory and the application to develop sophisticated simulation strategies that solve difficult performance verification challenges. These strategies may involve applying RF simulators to analog and mixed-signal circuits to extract information that is otherwise not possible to get, replacing large blocks of transistor-level circuitry with behavioral models to speed up the simulation, carefully configuring the simulator to avoid potential sources of error, or performing sophisticated analysis of the simulation results to extract some metric of performance. The result is that you learn new approaches to performing simulations that would otherwise seem impossible.
Our Philosophy
- We work jointly with designers.
- We adapt the methodology to fit your appetite for change.
- Our methodology works with either a bottom-up or top-down design style.
- We provide value at all times, often times in unexpected ways.
- We minimize interference to assure that no errors are created and the design process is not slowed by our presence.
- We always help designers anyway we can.
- Our focus is on teaching, but we will also help with the work as needed.
Key Benefits
- Complete consistency between specification, HDL hand off models, and schematics throughout the design process.
- A methodology based on careful verification, modeling, and simulation planning and reviews.
- Automated regression testing with simple pass/fail results.
- Substantial increase in the speed and accuracy of simulations.
- An adoption plan tailored to your needs and experience.
- The ability to perform simulations that might otherwise seem impossible.
How can you benefit from this approach? Read on ...
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