Summit Lake, near Agnew Pass on the Pacific Crest Trail
What do we do?
We help design teams overcome difficult verification challenges. Those challenges can involve either functional or performance verification. A difficult functional verification problem might be assuring that a mixed-signal circuit consisting of tens or hundreds of thousands of transistors with multiple ΔΣ converters operates correctly in each of its thousands of distinct operating modes. A difficult performance verification might be assuring that a large behaviorally complex circuit meets some demanding specification, such as a SerDes operating with a bit-error rate of less than 10–18.
How do we do it?
To functionally verify a complex mixed-signal design we teach a methodology based on modeling, mixed-level simulation, and comprehensive regression testing that provides verification of the specification, the model, and the implementation that is traceable to the transistor level.
For performance verification we employ a deep knowledge of the simulators, the modeling languages, the circuits, and the measurements to create insightful and efficient techniques for extracting the desired performance results from simulation.
The Result
- The performance of the design is known.
- The implementation matches the specification.
- The HDL hand-off model matches the implementation.
- All modes and settings are verified.
- Regression testing occurs throughout design process.
Indications That You Could Use Our Help
- You are running week-long simulations.
- You routinely have to turn a design because of simple functional errors.
- You go to silicon after testing only one or two modes or settings out of thousands.
- You need to develop a Verilog model of your analog IP, but you don't know how to assure it is completely faithful, or the consequences of any discrepancies.
- You made a chip where a block cannot operate without a signal supplied by another block, but that block depends on a signal from the first block, and neither start up.
- Despite being disappointed in the past, you are counting on as yet unreleased 'fast SPICE' simulators to solve your verification problems.
- You have analog designers creating control logic within the analog section.
- You are wondering if you can really trust the model you are getting from your IP supplier.
- You think modeling may be the solution to your problems, but you do not know how to get started.
- You have a performance specifications you cannot verify through simulation.
What are the challenges? Read on ...
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